$ whois verilog

Verilog

first released in 1984 · by Prabhu Goel, Phil Moorby, Chi-Lai Huang

$ guessprog --inspect verilog

year: 1984
paradigm: declarative
family: c like
memory: none
binding: static
safety: weak

VERILOG(7)

AUTHORS: Prabhu Goel, Phil Moorby, Chi-Lai Huang
HISTORY: Phil Moorby, Prabhu Goel and Chi-Lai Huang created Verilog around 1984 at Gateway Design Automation, as a language to simulate digital circuits. Cadence bought Gateway in 1990 and opened up the language to fight the rise of VHDL, and it became the IEEE 1364 standard in 1995. Where VHDL borrowed Ada's verbosity and strict types, Verilog went for a terse, C-like syntax and lets values of different widths mix silently. Its successor SystemVerilog absorbed it into the IEEE 1800 standard in 2009.
USAGE: Verilog and SystemVerilog are the dominant hardware description languages in the chip industry, used to design and verify CPUs, GPUs, ASICs and FPGA logic. Code describes hardware that runs in parallel, not instructions executed one after the other.
SEE ALSO: Verilog on Wikipedia ↗

$ cat counter.v

// 8-bit counter with synchronous reset
module counter (
    input  wire       clk,
    input  wire       reset,
    output reg  [7:0] count
);
    always @(posedge clk) begin
        if (reset)
            count <= 8'd0;
        else
            count <= count + 1;  // wraps around at 255
    end
endmodule